Michael C. Fairman

Software Designer/Developer

20+ years of successful software, hardware, and firmware development across a wide variety of products and platforms. Team player and project leader with excellent communication skills and a balanced, pragmatic mindset.

Languages: Ruby, Javascript, Perl, C, Assembly    Platforms: OS X, Linux, Embedded
Frameworks/Tools: Rails, jQuery, Haml, Coda, bash, rake, git, mySQL

Implemented motion-processing and audio mixing/playback algorithms in DSP assembly language on CSR BlueCore platform.

Created compute-farm infrastructure used by engineering departments worldwide, transforming development process from expensive desktop workstation model to efficient network-computing flow. System provided virtualized access to resources including CPUs, OSes, applications/tools, thin-client display terminals, and JTAG test nodes. Interfaces included web front-end with process control and result visualizations, command-line, Perl and SQL.

Integrated source control, bug tracking, wiki access and other services into development flow. Drove creation of infrastructure APIs and managed automated build/test processes. Promoted infrastructure adoption among teams at multiple sites.

Developed GUI framework for SOPC Builder and Nios products. Framework allowed developers to implement user interfaces for their hardware IP modules using simple layout directives, avoiding the need for custom code. Used by customers, third-party developers and internally for product development.

Developed SignalTap embedded logic analyzer GUI and JTAG control features. Product was first of its kind to allow capture of arbitrary internal FPGA signals, revolutionizing the on-chip debug and verification process.

Managed source control, product builds and final release packaging for Nios and SOPC Builder projects.

Managed software and QA teams in Santa Cruz office.

Received five US patents: #6754862: Gaining access to internal nodes in a PLD, #6976239: Methods and apparatus for implementing parameterizable processors and peripherals, #7000161: Reconfigurable programmable logic system with configuration recovery mode, #7225285: Assigning interrupts in multi-master systems, #7010666: Methods and apparatus for memory map generation on a programmable chip.

Developed Pod-A-Lyzer(tm) handheld logic analyzer firmware and application software. User interface provided fast pan/zoom of captured waveforms and easy-to-use bussing/un-bussing and signal assignment facilities.

Developed packet capture/disassembly layer atop logic analyzer functionality for CAN-bus and several DSP/microcontroller families.

Developed Silicon Explorer(tm) II logic analyzer firmware and application for Actel devices.

Developed firmware and host control software for Altera MasterBlaster(tm) JTAG device.

Worked on QuickDraw GX system software. Wrote bitmap drawing code, shape-hierarchy code, region operations, and matrix math routines. Also wrote graphics demos and games to excersize the platform.

Wrote clones of MS-DOS utilities (mode, format, fdisk) and video drivers for PC emulation platform which ran on Victor 9000 hardware. Created several graphics demos and games for the Victor and early IBM PC platform.

Studied Electrical Engineering program for three years, focusing on Embedded System Design.